1. Field of the Disclosure
The present disclosure relates to a method of fabricating a semiconductor device and, more particularly, to a method of fabricating a semiconductor device having a self-aligned cell diode and a method of fabricating a phase change memory device using the same.
2. Description of the Related Art
Phase change memory devices are widely used as non-volatile semiconductor memory devices. As non-volatile memory devices, phase change memory devices retain store data even in the event of a power loss. Usually, a phase change memory device includes a plurality of phase change memory cells. Each phase change memory cell may include a current switching device and a data storage element that are electrically connected with each other. In particular, the data storage element may have a lower electrode and an upper electrode. The lower electrode of the data storage element may electrically connect with the current switching device. Furthermore, the upper and lower electrodes may have a phase change material pattern therebetween
The lower electrode generally acts as a heater in the phase change memory device. Accordingly, when a current flows from the current switching device to the data storage element, the lower electrode may act as a heater to generate Joule heat at a contact surface of the phase change material. This generated Joule heat may cause the phase change material to be converted to an amorphous state or a crystalline state.
FIGS. 1A and 2A are plan views illustrating a conventional method of fabricating a phase change memory device, and FIGS. 1B and 2B are cross-sectional views showing a phase change memory device taken along line I-I′ of FIG. 1A and line II-II′ of FIG. 2A, respectively.
Referring to FIGS. 1A and 1B, a semiconductor substrate 10 may include an active region 12 and an isolation layer 14. The isolation layer 14 may be formed in the semiconductor substrate 10 to define or surround the active region 12. Furthermore, a word line 13 may be formed in or on the active region 12. The word line 13 may be a diode including a conductive pattern structure on the active region 12 or a impurity diffusion region in the active region 12. Also, a lower insulating layer 16 may be formed over the semiconductor substrate 10.
The lower insulating layer 16 may have at least one cell contact hole 18. The cell contact hole 18 may be formed by using well known photolithography and etching processes. In addition, the cell contact hole 18 may penetrate the lower insulating layer 16 to expose the word line 13. The cell contact hole 18 may have a circle shape in a plan view as shown in FIG. 1A.
Referring to FIGS. 2A and 2B, a cell diode 20 may be formed to partly fill the cell contact hole 18. The cell diode 20 may have a first semiconductor pattern 20a and a second semiconductor pattern 20b. Furthermore, the first and second semiconductor patterns 20a and 20b may be of conductive types that are different from each other. Moreover, a cell diode electrode 22 and a lower electrode 24 may be sequentially formed to sufficiently fill the cell contact hole 18 on the second semiconductor pattern 20b. Next, a phase change material pattern 26 may be formed on the lower insulating layer 16 to contact the lower electrode 24. In addition, an upper insulating layer 30 may be formed on the lower insulating layer 16 to cover the phase change material pattern 26. The upper insulating layer 30 may have an upper electrode 28. Furthermore, the upper electrode 28 may penetrate the upper insulating layer 30 to contact the phase change material pattern 26. In addition, a bit line 32 is formed on the upper insulating layer 30 to contact the upper electrode 28.
The cell diode electrode 22, the lower electrode 24, the upper electrode 28, and the bit line 32 may form a selective phase change memory cell 35 in the phase change memory device together with the phase change material pattern 26. The phase change material pattern 26 may be formed using a chalcogenide material layer. The chalcogenide material layer may formed of a material such as, for example, a germanium stibium tellurium (GeSbTe) layer (hereinafter, referred to as a GST layer).
During the operation of the phase change memory device, a current flows toward the phase change material pattern 26 through the lower electrode 24 or the upper electrode 28. If current flows through the lower electrode 24, the current may generate Joule heat at a contacting surface between the lower electrode 24 and the phase change material pattern 26. This Joule heat may change the existing state of the phase change material pattern 26 to a crystalline state or an amorphous state. Furthermore, by changing the state of the phase change material pattern 26, the desired data is stored in the phase change memory cell.
While the conventional semiconductor memory device fabrication method may be used to fabricate a phase change memory device, it suffers from various shortcomings. For example, in the conventional method, the cell contact hole 18 may misalign with the word line 13 such that it deviates from the word line 13. This misalignment may occur due to defects in the photolithography process. Accordingly, a poor contact may occur between the word line 13 and the cell diode 20 in the cell contact hole 18.
For example, as shown in FIGS. 1A and 1B, the cell contact hole 18 may only partially overlap the word line 13 because of defects in the photolithography. Due to only this partial overlap, the cell diode 20 may have a relatively small contacting surface with the word line 13 as compared to the desirable scenario of having the cell contact hole 18 sufficiently overlap the word line 13. Because of this relatively small contact surface between the cell diode 20 and the word line 13, the series resistance between the word line 13 and the lower electrode 22 may increase through the cell contact hole 18. This increased resistance between the word line 13 and the lower electrode 22 may have undesirable effects on the phase change memory device 35.
The present disclosure is directed towards overcoming one or more limitations of the conventional semiconductor device fabrication method.